View 25C640_3494330.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1997 microchip technology inc. preliminary ds21223a-page 1 m 25aa640/25lc640/25C640 device selection table features low power cmos technology - write current: 3 ma typical - read current: 500 m a typical - standby current: 500 na typical 8192 x 8 bit organization 32 byte page write cycle time: 5ms max. self-timed erase and write cycles block write protection - protect none, 1/4, 1/2, or all of array built-in write protection - power on/off data protection circuitry - write enable latch - write protect pin sequential read high reliability - endurance: 1m cycles (guaranteed) - data retention: > 200 years - esd protection: > 4000 v 8-pin pdip, soic, and tssop packages temperature ranges supported: description the microchip technology inc. 25aa640/25lc640/ 25C640 (25xx640 * ) is a 64k bit serial electrically eras- able prom. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. package types block diagram part number v cc range max clock frequency temp ranges 25aa640 1.8-5.5v 1 mhz c,i 25lc640 2.5-5.5v 2 mhz c,i 25C640 4.5-5.5v 3 mhz c,i,e - commercial: (c) 0 c to +70 c - industrial: (i) -40 c to +85 c - automotive: (e) (25C640) -40 c to +125 c 25xx640 tssop 1 2 3 4 8 7 6 5 sck si v ss wp hold v cc cs so 25xx640 pdip/soic 1 2 3 4 8 7 6 5 v cc hold sck si cs so wp v ss si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss 64k spi bus serial eeprom *25xx640 is used in this document as a generic part number for the 25aa640/25lc640/25C640 devices. spi is a trademark of motorola.
25aa640/25lc640/25C640 ds21223a -page 2 preliminary ? 1997 microchip technology inc. 1.0 electrical c haracteristics 1.1 maxim um ratings* vcc ................................................................................... 7.0v all inputs and outputs w .r .t. vss .................. -0.6v to vcc+1.0v stor age temper ature ....................................... -65?c to 150?c ambient temper ature under bias ..................... -65?c to 125?c solder ing temper ature of leads (10 seconds) ............. +300?c esd protection on all pins ................................................. 4kv *notice: stresses abo v e those listed under ?axim um r atings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or an e xtended per iod of time ma y aff ect de vice reliability t able 1-1: pin function t able figure 1-1: ac test cir cuit 1.2 a c t est conditions name function cs chip select input so ser ial data output si ser ial data input sck ser ial cloc k input wp wr ite protect pin v ss ground v cc supply v oltage hold hold input a c w a v ef or m: v lo = 0.2v v h i = v cc - 0.2v ( note 1 ) v h i = 4.0v ( note 2 ) timing measurement ref erence le v el input 0.5 v cc output 0.5 v cc note 1: f or v cc 4.0v 2: f or v cc > 4.0v v cc s o 100 pf 1.8 k 2.25 k t able 1-2: dc c haracteristics all par ameters apply o v er the speci ed oper ating r anges unless otherwise noted. commercial (c): t amb = 0 c to +70 c v cc = 1.8v to 5.5v industr ial (i): t amb = -40 c to +85 c v cc = 1.8v to 5.5v a utomotiv e (e): t amb = -40 c to +125 c v cc = 4.5v to 5.5v ( 25C640 only) p arameter symbol min max units t est conditions high le v el input v oltage v ih 1 2.0 v cc +1 v v cc 3 2.7v (note) v ih 2 0.7 v cc v cc +1 v v cc < 2.7v (note) lo w le v el input v oltage v il 1 -0.3 0.8 v v cc 3 2.7v (note) v il 2 -0.3 0.3 v cc v v cc < 2.7v (note) lo w le v el output v oltage v ol 0.4 v i ol = 2.1 ma v ol 0.2 v i ol = 1.0 ma, v cc < 2.5v high le v el output v oltage v oh v cc -0.5 v i oh =-400 m a input leakage current i li -10 10 m a cs = v cc , v in = v ss to v cc output leakage current i lo -10 10 m a cs = v cc , v out = v ss to v cc inter nal capacitance (all inputs and outputs) c int 7 pf t amb = 25?c , clk = 1.0 mhz, v cc = 5.0v (note) oper ating current i cc read 1 500 ma m a v cc = 5.5v ; f clk =3.0 mhz; so = open v cc = 2.5v ; f clk =2.0 mhz; so = open i cc wr ite 5 3 ma ma v cc = 5.5v v cc = 2.5v standb y current i ccs 5 1 m a m a cs = vcc = 5.5v , inputs tied to v cc or v ss cs = vcc = 2.5v , inputs tied to v cc or v ss note: this par ameter is per iodically sampled and not 100% tested.
25aa640/25lc640/25C640 ? 1997 microchip technology inc. preliminary ds21223a -page 3 t able 1-3: ac c haracteristics all par ameters apply o v er the speci ed oper ating r anges unless otherwise noted. commercial (c): t amb = 0 c to +70 c v cc = 1.8v to 5.5v industr ial (i): t amb = -40 c to +85 c v cc = 1.8v to 5.5v a utomotiv e (e): t amb = -40 c to +125 c v cc = 4.5v to 5.5v ( 25C640 only) p arameter symbol min max units t est conditions cloc k f requency f clk 3 2 1 mhz mhz mhz v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs setup time t css 100 250 500 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs hold time t csh 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cs disab le time t csd 500 ns data setup time t su 30 50 50 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v data hold time t hd 50 100 100 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v clk rise time t r 2 m s (note 1) clk f all time t f 2 m s (note 1) cloc k high time t hi 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cloc k lo w time t lo 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v cloc k dela y time t cld 50 ns cloc k enab le time t cle 50 ns output v alid from cloc k lo w t v 150 250 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v output hold time t ho 0 ns (note 1) output disab le time t dis 200 250 500 ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) hold setup time t hs 100 100 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v hold hold time t hh 100 100 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v hold lo w to output high-z t hz 100 150 200 ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) hold high to output v alid t hv 100 150 200 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v inter nal wr ite cycle time t wc 5 ms endur ance 1m e/w cycles (note 2) note 1: this par ameter is per iodically sampled and not 100% tested. 2: this par ameter is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c application, please consult the t otal endur ance model which can be obtained on microchip s bbs or w ebsite .
25aa640/25lc640/25C640 ds21223a -page 4 preliminary ? 1997 microchip technology inc. figure 1-2: hold timing figure 1-3: serial input timing figure 1-4: serial output timing cs sck so si hold t hh t hs t hs t hh t hv t hz don? care t su high impedance n+2 n+1 n n-1 n n+2 n+1 n n n-1 cs sck si so t css t hd tsu t f t r t csd t cld t csh lsb in msb in high impedance t cle mode 1,1 mode 0,0 cs sck so t lo t hi t ho t v msb out lsb out t csh t dis don? care si mode 1,1 mode 0,0
25aa640/25lc640/25C640 ? 1997 microchip technology inc. preliminary ds21223a -page 5 2.0 pin descriptions 2.1 chip select ( cs ) a lo w le v el on this pin selects the de vice . a high le v el deselects the de vice and f orces it into standb y mode . ho w e v er , a prog r amming cycle which is already initi- ated or in prog ress will be completed, regardless of the cs input signal. if cs is brought high dur ing a prog r am cycle , the de vice will go in standb y mode as soon as the prog r amming cycle is complete . as soon as the de vice is deselected, so goes to the high impedance state , allo wing m ultiple par ts to share the same spi b us . a lo w to high tr ansition on cs after a v alid wr ite sequence initiates an inter nal wr ite cycle . after po w er- up , a high to lo w tr ansition on cs is required pr ior to an y sequence being initiated. 2.2 serial input (si) the si pin is used to tr ansf er data into the de vice . it receiv es instr uctions , addresses , and data. data is latched on the r ising edge of the ser ial cloc k. 2.3 serial output (so) the so pin is used to tr ansf er data out of the 25xx640 . dur ing a read cycle , data is shifted out on this pin after the f alling edge of the ser ial cloc k. 2.4 serial cloc k (sck) the sck is used to synchroniz e the comm unication betw een a master and the 25xx640 . instr uctions , addresses , or data present on the si pin are latched on the r ising edge of the cloc k input, while data on the so pin is updated after the f alling edge of the cloc k input. 2.5 write pr otect ( wp ) this pin is used in conjunction w ith the wpen bit in the status register to prohibit wr ites to the non-v olatile bits in the status register . when wp is lo w and wpen is high, wr iting to the non-v olatile bits in the status regis- ter is disab led. all other oper ations function nor mally . when wp is high, all functions , including wr ites to the non-v olatile bits in the status register oper ate nor mally . if the wpen bit is set, wp lo w dur ing a status register wr ite sequence will disab le wr iting to the status regis- ter . if an inter nal wr ite cycle has already begun, wp going lo w will ha v e no eff ect on the wr ite . the wp pin function is b loc k ed when the wpen bit in the status register is lo w . this allo ws the user to install the 25aa640/25lc640/25C640 in a system with wp pin g rounded and still be ab le to wr ite to the status reg- ister . the wp pin functions will be enab led when the wpen bit is set high. 2.6 hold ( hold ) the hold pin is used to suspend tr ansmission to the 25xx640 while in the middle of a ser ial sequence with- out ha ving to re-tr ansmit the entire sequence o v er at a later time . it m ust be held high an y time this function is not being used. once the de vice is selected and a ser ial sequence is underw a y , the hold pin ma y be pulled lo w to pause fur ther ser ial comm unication with- out resetting the ser ial sequence . the hold pin m ust be brought lo w while sck is lo w , otherwise the hold function will not be in v ok ed until the ne xt sck high to lo w tr ansition. the 25xx640 m ust remain selected dur- ing this sequence . the si, sck, and so pins are in a high impedance state dur ing the time the par t is paused and tr ansitions on these pins will be ignored. t o resume ser ial comm unication, hold m ust be brought high while the sck pin is lo w , otherwise ser ial comm unication will not resume . lo w er ing the hold line at an y time will tr i-state the so line .
25aa640/25lc640/25C640 ds21223a -page 6 preliminary ? 1997 microchip technology inc. 3.0 functional description 3.1 principles of opera tion the 25xx640 is a 8192 b yte ser ial eepr om designed to interf ace directly with the ser ial p er ipher al interf ace (spi) por t of man y of toda y s popular microcontroller f amilies , including microchip s pic16c6x/7x micro- controllers . it ma y also interf ace with microcontrollers that do not ha v e a b uilt-in spi por t b y using discrete i/o lines prog r ammed proper ly with the softw are . the 25xx640 contains an 8-bit instr uction register . the par t is accessed via the si pin, with data being cloc k ed in on the r ising edge of sck. the cs pin m ust be lo w and the hold pin m ust be high f or the entire oper a- tion. t ab le 3-1 contains a list of the possib le instr uction b ytes and f or mat f or de vice oper ation. all instr uctions , addresses , and data are tr ansf erred msb rst, lsb last. data is sampled on the rst r ising edge of sck after cs goes lo w . if the cloc k line is shared with other per ipher al de vices on the spi b us , the user can asser t the hold input and place the 25xx640 in ?old mode . after releasing the hold pin, oper ation will resume from the point when the hold w as asser ted. 3.2 read sequence the par t is selected b y pulling cs lo w . the 8-bit read instr uction is tr ansmitted to the 25xx640 f ollo w ed b y the 16-bit address with the three msb s of the address being don? care bits . after the correct read instr uction and address are sent, the data stored in the memor y at the selected address is shifted out on the so pin. the data stored in the memor y at the ne xt address can be read sequentially b y contin uing to pro vide cloc k pulses . the inter nal address pointer is automatically incre- mented to the ne xt higher address after each b yte of data is shifted out. when the highest address is reached (1fffh), the address counter rolls o v er to address 0000h allo wing the read cycle to be contin ued inde nitely . the read oper ation is ter minated b y r aising the cs pin ( figure 3-1 ). 3.3 write sequence pr ior to an y attempt to wr ite data to the 25xx640 arr a y or status register , the wr ite enab le latch m ust be set b y issuing the wren instr uction ( figure 3-4 ). this is done b y setting cs lo w and then cloc king out the proper instr uction into the 25xx640 . after all eight bits of the instr uction are tr ansmitted, the cs m ust be brought high to set the wr ite enab le latch. if the wr ite oper ation is initiated immediately after the wren instr uction without cs being brought high, the data will not be wr itten to the arr a y because the wr ite enab le latch will not ha v e been proper ly set. once the wr ite enab le latch is set, the user ma y pro- ceed b y setting the cs lo w , issuing a wr ite instr uction, f ollo w ed b y the address , and then the data to be wr it- ten. up to 32 b ytes of data can be sent to the 25xx640 bef ore a wr ite cycle is necessar y . the only restr iction is that all of the b ytes m ust reside in the same page . a page address begins with xxx0 0000 and ends with xxx1 1111. if the inter nal address counter reaches xxx1 1111 and the cloc k contin ues , the counter will roll bac k to the rst address of the page and o v erwr ite an y data in the page that ma y ha v e been wr itten. f or the data to be actually wr itten to the arr a y , the cs m ust be brought high after the least signi cant bit (d0) of the n th data b yte has been cloc k ed in. if cs is brought high at an y other time , the wr ite oper ation will not be completed. ref er to figure 3-2 and figure 3-3 f or more detailed illustr ations on the b yte wr ite sequence and the page wr ite sequence respectiv ely . while the wr ite is in prog ress , the status register ma y be read to chec k the status of the wpen, wip , wel, bp1, and bp0 bits ( figure 3-6 ). a read attempt of a memor y arr a y location will not be possib le dur ing a wr ite cycle . when the wr ite cycle is completed, the wr ite enab le latch is reset. t able 3-1: instruction set instruction name instruction format description read 0000 0011 read data from memor y arr a y beginning at selected address write 0000 0010 wr ite data to memor y arr a y beginning at selected address wren 0000 0110 set the wr ite enab le latch (enab le wr ite oper ations) wrdi 0000 0100 reset the wr ite enab le latch (disab le wr ite oper ations) rdsr 0000 0101 read status register wrsr 0000 0001 wr ite status register
25aa640/25lc640/25C640 ? 1997 microchip technology inc. preliminary ds21223a -page 7 figure 3-1: read sequence figure 3-2: byte write sequence figure 3-3: pa g e write sequence so si sck cs 0 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 1 0 1 0 0 0 0 0 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 instr uction 16 bit address data out high impedance so si cs 0 0 0 0 0 0 0 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 instr uction 16 bit address data b yte high impedance t wc si cs 9 10 11 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 instr uction 16 bit address data b yte 1 sck 0 2 3 4 5 6 7 1 8 si cs 41 42 43 46 47 7 6 5 4 3 2 1 0 data b yte n (32 max) sck 32 34 35 36 37 38 39 33 40 7 6 5 4 3 2 1 0 data b yte 3 7 6 5 4 3 2 1 0 data b yte 2 44 45
25aa640/25lc640/25C640 ds21223a -page 8 preliminary ? 1997 microchip technology inc. 3.4 write enab le (wren) and write disab le (wrdi) the 25xx640 contains a wr ite enab le latch. see t ab le 3-3 f or the wr ite protect functionality matr ix. this latch m ust be set bef ore an y wr ite oper ation will be completed inter nally . the wren instr uction will set the latch, and the wrdi will reset the latch. the f ollo wing is a list of conditions under which the wr ite enab le latch will be reset: p o w er-up wrdi instr uction successfully e x ecuted wrsr instr uction successfully e x ecuted write instr uction successfully e x ecuted figure 3-4: write e n ab le sequence figure 3-5: write disab le sequence sck 0 2 3 4 5 6 7 1 si high impedance so cs 0 1 0 0 0 0 0 1 sck 0 2 3 4 5 6 7 1 si high impedance so cs 0 1 0 0 0 0 0 1 0
25aa640/25lc640/25C640 ? 1997 microchip technology inc. preliminary ds21223a -page 9 3.5 r ead status register (rdsr) the rdsr instr uction pro vides access to the status register . the status register ma y be read at an y time , e v en dur ing a wr ite cycle . the status register is f or mat- ted as f ollo ws: the write-in-pr ocess (wip) bit indicates whether the 25xx640 is b usy with a wr ite oper ation. when set to a ? a wr ite is in prog ress , when set to a ? no wr ite is in prog ress . this bit is read only . the write enab le latc h (wel) bit indicates the status of the wr ite enab le latch. when set to a ? the latch allo ws wr ites to the arr a y and status register , when set to a ? the latch prohibits wr ites to the arr a y and status register . the state of this bit can alw a ys be updated via the wren or wrdi commands regardless of the state of wr ite protection on the status register . this bit is read only . the bloc k pr otection (bp0 and bp1) bits indicate which b loc ks are currently wr ite protected. these bits are set b y the user issuing the wrsr instr uction. these bits are non-v olatile . see figure 3-6 f or rdsr timing sequence 3.6 write status register(wrsr) the wrsr instr uction allo ws the user to select one of f our le v els of protection f or the arr a y b y wr iting to the appropr iate bits in the status register . the arr a y is divided up into f our segments . the user has the ability to wr ite protect none , one , tw o , or all f our of the seg- ments of the arr a y . the par titioning is controlled as illustr ated in t ab le 3-2 . the write pr otect enab le (wpen) bit is a non-v olatile bit that is a v ailab le as an enab le bit f or the wp pin. the wr ite protect ( wp ) pin and the wr ite protect enab le (wpen) bit in the status register control the prog r ammab le hardw are wr ite protect f eature . hard- w are wr ite protection is enab led when wp pin is lo w and the wpen bit is high. hardw are wr ite protection is disab led when either the wp pin is high or the wpen bit is lo w . when the chip is hardw are wr ite protected, only wr ites to non-v olatile bits in the status register are disab led. see t ab le 3-3 f or a matr ix of functionality on the wpen bit. see figure 3-7 f or wrsr timing sequence t able 3-2: arra y pr otection figure 3-6: read status register sequence figure 3-7: write status register sequence 7 6 5 4 3 2 1 0 wpen x x x bp1 bp0 wel wip bp1 bp0 arra y ad dresses write pr otected 0 0 none 0 1 upper 1/4 (1800h - 1fffh) 1 0 upper 1/2 (1000h - 1fffh) 1 1 all (0000h - 1fffh) so si cs 9 10 11 12 13 14 15 1 1 0 0 0 0 0 0 7 6 5 4 2 1 0 instr uction data from status register high impedance sck 0 2 3 4 5 6 7 1 8 3 so si cs 9 10 11 12 13 14 15 0 1 0 0 0 0 0 0 7 6 5 4 2 1 0 instr uction data to status register high impedance sck 0 2 3 4 5 6 7 1 8 3
25aa640/25lc640/25C640 ds21223a -page 10 preliminary ? 1997 microchip technology inc. 3.7 data pr otection the f ollo wing protection has been implemented to pre- v ent inadv er tent wr ites to the arr a y: the wr ite enab le latch is reset on po w er-up . a wr ite enab le instr uction m ust be issued to set the wr ite enab le latch. after a b yte wr ite , page wr ite , or status register wr ite , the wr ite enab le latch is reset. cs m ust be set high after the proper n umber of cloc k cycles to star t an inter nal wr ite cycle . access to the arr a y dur ing an inter nal wr ite cycle is ignored and prog r amming is contin ued. 3.8 p o wer on state the 25xx640 po w ers on in the f ollo wing state: the de vice is in lo w po w er standb y mode ( cs = 1). the wr ite enab le latch is reset. so is in high impedance state . a high to lo w tr ansition on cs is required to enter the activ e state . . t able 3-3: write pr otect functionality matrix wpen wp wel pr otected bloc ks unpr otected bloc ks status register x x 0 protected protected protected 0 x 1 protected wr itab le wr itab le 1 lo w 1 protected wr itab le protected x high 1 protected wr itab le wr itab le
25aa640/25lc640/25C640 ? 1997 microchip technology inc. preliminary ds21223a -page 11 25aa640/25lc640/25C640 pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = tssop , 8-lead t emperature rang e: blank = 0 c to +70 c i = ?0 c to +85 c e = ?0 c to +125 c de vices: 25aa640 64k bit 1.8v spi ser ial eepr om 25aa640 t 64k bit 1.8v spi ser ial eepr om t ape and reel 25aa640 x 64k bit 1.8v spi ser ial eepr om in alter nate pinout (st only) 25aa640 xt 64k bit 1.8v spi ser ial eepr om in alter nate pinout t ape and reel (st only) 25lc640 64k bit 2.5v spi ser ial eepr om 25lc640 t 64k bit 2.5v spi ser ial eepr om t ape and reel 25lc640 x 64k bit 2.5v spi ser ial eepr om in alter nate pinout (st only) 25lc640 xt 64k bit 2.5v spi ser ial eepr om in alter nate pinout t ape and reel (st only) 25C640 64k bit 5.0v spi ser ial eepr om 25C640 t 64k bit 5.0v spi ser ial eepr om t ape and reel 25C640 x 64k bit 5.0v spi ser ial eepr om in alter nate pinout (st only) 25C640 xt 64k bit 5.0v spi ser ial eepr om in alter nate pinout t ape and reel (st only) 25xx640 /p data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required) .
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life sup port systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the m icrochip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21223a-page 12 ? 1997 microchip technology inc. m all rights reserved. ? 1997, microchip technology incorporated, usa. 9/97 printed on recycled paper. americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-4036 fax: 91-80-559-9840 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology taiwan singapore branch 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2-717-7175 fax: 886-2-545-0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44-1628-851077 fax: 44-1628-850259 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 8/29/97 w orldwide s ales & s ervice

▲Up To Search▲

Price & Availability of 25C640

	To Download 25C640 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .